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RTL Senior Engineer
职位:RTL Senior Engineer
工作地点:Orange County, California, USA
招聘人数:1 人
工作年限:5 年
语言要求:英文精通
学历:硕士
工作职责:
  

You will be responsible for RTL designs like bus, memory controller, processor integration. You will work with the architects, ASIC designers and CAD automation to plan and execute verification and automation.

Required:  Legally authorized to work in the US


任职要求:
  

 Strong RTL design skills

   Have good understanding of digital design flow (CDC, Low Power, HDL Simulation, Synthesis)

   Have know-how of ARM Cortex-A series Cores

 Experience in design of bus, protocol bridges, memory controllers, processors

 Strong working knowledge of Verilog VHDL

 Proficient in debugging complicated designs

Minimum Qualifications:

 Bachelor’s degree in Science, Engineering, or related field.

 5+ years ASIC design or related work experience.


  • RTL Senior Engineer
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