任职要求:
Strong RTL design skills
Have good understanding of digital design flow (CDC, Low Power, HDL Simulation, Synthesis)
Have know-how of ARM Cortex-A series Cores
Experience in design of bus, protocol bridges, memory controllers, processors
Strong working knowledge of Verilog VHDL
Proficient in debugging complicated designs
Minimum Qualifications:
Bachelor’s degree in Science, Engineering, or related field.
5+ years ASIC design or related work experience.